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W9725G6KB
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK /CLK
CMD
Active
A-Bank
Read
A-Bank
Write
A-Bank
WL=RL-1=4
AL=2
CL=3
DQS/DQS
≥ t RCD
RL=AL+CL=5
DQ
Dout0 Dout1
Dout2 Dout3
Din0
Din1
Din2
Din3
[AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4]
Figure 14 – Example 1: Read followed by a write to the same bank,
where AL = 2 and CL = 3, RL = (AL + CL) = 5, WL = (RL - 1) = 4, BL = 4
-1
0
1
2
3
4
5
6
7
8
9
10
11
12
CLK/CLK
AL=0
CMD
Active
A-Bank
Read
A-Bank
Write
A-Bank
WL=RL-1=2
CL=3
DQS/DQS
≥ t RCD
RL=AL+CL=3
DQ
Dout0
Dout1 Dout2 Dout3
Din0
Din1
Din2
Din3
AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4]
Figure 15 – Example 2: Read followed by a write to the same bank,
where AL = 0 and CL = 3, RL = (AL + CL) = 3, WL = (RL - 1) = 2, BL = 4
8.4.2
Burst mode operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or
from memory locations (read cycle). The parameters that define how the burst mode will operate are
burst sequence and burst length. The DDR2 SDRAM supports 4 bit and 8 bit burst modes only. For 8
bit burst mode, full interleave address ordering is supported, however, sequential address ordering is
nibble based for ease of implementation. The burst length is programmable and defined by MR A[2:0].
The burst type, either sequential or interleaved, is programmable and defined by MR [A3]. Seamless
burst read or write operations are supported.
Publication Release Date: Sep. 03, 2012
- 24 -
Revision A03
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